1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM incorporating a test mechanism.
2. Description of the Background Art
Manufactured DRAM chips are shipped after testing all memory cells to verify normal writing and reading by means of a tester. As the memory capacity of DRAM chips tends to increase, the testing time increases. For example, in a 64M (megabit) DRAM chips, a simple test procedure of writing "1" in all memory cells, reading "1" from all memory cells, writing "0" in all memory cells, and reading "0" from all memory cells in a cycle time of 90 ns takes 90.times.19.sup.-9 .times.4.times.64.times.(1024).sup.2 =24 seconds.
Actually, testing in a test procedure adding various inspection items takes about 300 seconds. However, since DRAM chips must be mass produced at a rate of several million per month, the processing capacity is raised and the testing time is shortened by measuring plural DRAM chips simultaneously.
FIG. 22 shows a configuration for simultaneous parallel measurement of plural DRAM chips. In FIG. 22, n test pieces, DRAM chips M1 to Mn, are connected in parallel to a tester 70. The tester 70 possesses n signal drivers D11 to D1n, and n data judging circuits J11 to J1n. The signal driver D11 and data judging circuit J11 are connected to DQ pin of the DRAM chip M1, and write data is applied to the DQ pin of the DRAM chip M1 in a write cycle, and the data judging circuit J11 judges if the DRAM chip M1 outputs correct read data in a read cycle. Similarly, thereafter, the signal driver D12 and data judging circuit J12 are connected to DQ pin of the DRAM chip M2, and signal driver D1n and data judging circuit J1n to DQ pin of the DRAM chip Mn, sequentially.
The tester 70 is also designed to give specific signals to bar RAS pin, bar CAS pin, bar OE pin, bar WE pin and address signal pins of individual DRAM chips M which are not shown in the drawing.
Hitherto, as mentioned above, using a tester having as many signal drivers and data judging circuits as the number of n DRAM chips to be tested, by testing n DRAM chips simultaneously, the processing capacity was raised and the testing time was shortened. However, the tester having a plurality of data judging circuits is expensive, and the testing cost tended to increase.